Taiwan Semiconductor Manufacturing Company Limited (TSMC) held its 2024 North America Technology Symposium today (24th local time in the United States), revealing its latest process technology, advanced packaging technology, and three-dimensional integrated circuit (3D IC) technology to drive innovation in the next generation of Artificial Intelligence (AI). With this leading semiconductor technology, TSMC aims to propel the next generation of AI innovation. TSMC unveiled its groundbreaking TSMC A16™ technology, which combines leading-edge nanosheet transistors and innovative backside power rail solutions to significantly enhance logic density and efficiency. It is expected to enter mass production in 2026. Additionally, TSMC introduced the System-on-Wafer (TSMC-SoW™) technology, which offers revolutionary wafer-level performance advantages to meet the future demands of AI in ultra-large-scale data centers.
This year marks the 30th anniversary of TSMC's North America Technology Symposium. Attendance has grown from less than 100 guests 30 years ago to over 2,000 this year. Held in Santa Clara, California, the North America Technology Symposium kicks off a series of global technology forums scheduled for the coming months. The symposium also features an innovation zone showcasing the technical achievements of emerging customers.
Dr. Wei Zhejia, President of TSMC, stated, "We live in a world empowered by AI, where AI functionality is not only deployed in data centers but also embedded in personal computers, mobile devices, automobiles, and even the Internet of Things. TSMC provides customers with the most comprehensive technology, from the world's most advanced silicon chips to the widest range of advanced packaging combinations and 3D IC platforms, as well as special process technologies that bridge the digital and physical worlds, to realize their vision for AI."
The new technologies unveiled at the symposium include:
TSMC A16™ Technology: Building on the industry-leading N3E technology entering mass production and the N2 technology expected to enter mass production in the second half of 2025, TSMC introduced the new A16 technology. A16 integrates TSMC's Super Power Rail architecture with nanosheet transistors and is scheduled for mass production in 2026. The Super Power Rail technology moves the power network to the backside of the wafer, freeing up layout space on the front side for more signal networks, thus enhancing logic density and efficiency. A16 is suitable for high-performance computing (HPC) products with complex signal routing and dense power networks. Compared to TSMC's N2P process, A16 offers an 8-10% speed increase at the same Vdd (operating voltage), a 15-20% power reduction at the same speed, and a chip density increase of up to 1.10 times to support data center products.
TSMC's innovative NanoFlex™ technology supports nanosheet transistors: TSMC's upcoming N2 technology will be paired with TSMC NanoFlex technology, showcasing TSMC's breakthroughs in design technology co-optimization. TSMC NanoFlex provides chip designers with flexible N2 standard components, the fundamental building blocks of chip design. Lower-height components save space and offer higher power efficiency, while taller components maximize performance. Customers can optimize high-low component combinations within the same design block to achieve the best balance between power consumption, performance, and area in applications.
N4C Technology: TSMC announced the introduction of advanced N4C technology to address a broader range of applications. Building on the N4P technology, N4C reduces chip costs by up to 8.5% and features a lower threshold, with mass production expected in 2025. N4C provides area-efficient baseline silicon IP and design rules that are fully compatible with the widely adopted N4P, enabling customers to easily transition to N4C. Smaller chip sizes and increased yields offer cost-effective options for value-centric products, upgrading to TSMC's next advanced technology.
CoWoS®, System Integration Chips, and System-on-Wafer (TSMC-SoW™): TSMC's CoWoS® is a key enabling technology for the AI revolution, allowing customers to place more processor cores and high-bandwidth memory (HBM) side by side on a single interposer. Meanwhile, TSMC's System Integration Chips (SoIC) have become the leading solution for 3D chip stacking. Customers increasingly adopt CoWoS with SoIC and other components to achieve ultimate system-level packaging integration.
TSMC's System-on-Wafer technology offers an innovative option, allowing 12-inch wafers to accommodate a large number of chips, providing more computing power, significantly reducing data center footprint, and increasing energy efficiency by orders of magnitude per watt. TSMC's first SoW product to enter mass production utilizes an integrated fan-out (InFO) technology with a focus on logic chips, while a chip-stacked version using CoWoS technology is expected to be ready by 2027, integrating SoIC, HBM, and other components to create a powerful wafer-level system rivaling data center server racks or even entire servers.
Silicon Photonics Integration: TSMC is developing the Compact Universal Photon Engine (COUPE™) technology to support the explosive growth in data transmission brought about by the AI boom. COUPE utilizes SoIC-X chip stacking technology to stack bare dies of electronics on top of bare dies of photonics, providing the lowest possible resistance and higher energy efficiency at the die-to-die interface compared to traditional stacking methods. TSMC expects to complete COUPE verification with small form-factor pluggable connectors by 2025, followed by the integration of CoWoS packaging into Co-Packaged Optics (CPO) in 2026, bringing optical connectivity directly into packaging.
Advanced Packaging for Automotive: Following the introduction of the N3AE process supporting automotive customers and early adoption in 2023, TSMC continues to meet the increasing demand for higher computing power in the automotive industry by integrating advanced chips and packaging. TSMC is developing InFO-oS and CoWoS-R solutions to support advanced driver assistance systems (ADAS), vehicle control, central computers, and other applications, with AEC-Q100 Level 2 verification expected to be completed in the fourth quarter of 2025.
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